TY - GEN
T1 - Web-enabled neuron model hardware implementation and testing
AU - Morgan, Fearghal
AU - Krewer, Finn
AU - Callaly, Frank
AU - Coffey, Aedan
AU - McGinley, Brian
N1 - Publisher Copyright:
Copyright © 2015 by SCITEPRESS - Science and Technology Publications, Lda. All rights reserved.
PY - 2015
Y1 - 2015
N2 - This paper presents a prototype web-based Graphical User Interface (GUI) platform for integrating and testing a system that can perform Low-Entropy Model Specification (LEMS) neural network description to Hardware Description Language (VHDL) conversion, and automatic synthesis and neuron implementation and testing on Field Programmable Gate Array (FPGA) testbed hardware. This system enables hardware implementation of neuron components and their connection in a small neural network testbed. This system incorporates functionality for automatic LEMS to synthesisable VHDL translation, automatic VHDL integration with FPGA logic to enable data I/O, automatic FPGA bitfile generation using Xilinx PlanAhead, automated multi- FPGA testbed configuration, neural network parameter configuration and flexible testing of FPGA based neuron models. The prototype UI supports clock step control and real-time monitoring of internal signals. References are provided to video demonstrations.
AB - This paper presents a prototype web-based Graphical User Interface (GUI) platform for integrating and testing a system that can perform Low-Entropy Model Specification (LEMS) neural network description to Hardware Description Language (VHDL) conversion, and automatic synthesis and neuron implementation and testing on Field Programmable Gate Array (FPGA) testbed hardware. This system enables hardware implementation of neuron components and their connection in a small neural network testbed. This system incorporates functionality for automatic LEMS to synthesisable VHDL translation, automatic VHDL integration with FPGA logic to enable data I/O, automatic FPGA bitfile generation using Xilinx PlanAhead, automated multi- FPGA testbed configuration, neural network parameter configuration and flexible testing of FPGA based neuron models. The prototype UI supports clock step control and real-time monitoring of internal signals. References are provided to video demonstrations.
KW - Biological neural networks
KW - Brain-inspired computation
KW - FPGA hardware neural networks
KW - Low entropy model specification (LEMS)
KW - VHDL
KW - Web-enabled neural capture
UR - https://www.scopus.com/pages/publications/84960468569
U2 - 10.5220/0005713001380145
DO - 10.5220/0005713001380145
M3 - Conference Publication
AN - SCOPUS:84960468569
T3 - NEUROTECHNIX 2015 - Proceedings of the 3rd International Congress on Neurotechnology, Electronics and Informatics
SP - 138
EP - 145
BT - NEUROTECHNIX 2015 - Proceedings of the 3rd International Congress on Neurotechnology, Electronics and Informatics
A2 - Faisal, Aldo
A2 - Krebs, Hermano Igo
A2 - Pedotti, Antonio
PB - SCITEPRESS
T2 - 3rd International Congress on Neurotechnology, Electronics and Informatics, NEUROTECHNIX 2015
Y2 - 16 November 2015 through 17 November 2015
ER -