TY - GEN
T1 - Overcome the limitations of performance parameters of on-chip antennas based on metasurface and coupled feeding approaches for applications in system-on-chip for THz integrated-circuits
AU - Alibakhshikenari, Mohammad
AU - Virdee, Bal S.
AU - See, Chan H.
AU - Abd-Alhameed, Raed A.
AU - Falcone, Francisco
AU - Limiti, Ernesto
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/12
Y1 - 2019/12
N2 - This paper proposes a new solution to improve the performance parameters of on-chip antenna designs on standard CMOS silicon (Si.) technology. The proposed method is based on applying the metasurface technique and exciting the radiating elements through coupled feed mechanism. The on-chip antenna is constructed from three layers comprising Si.-GND-Si. layers, so that the ground (GND) plane is sandwiched between two Si. layers. The silicon and ground-plane layers have thicknesses of 20mu m and 5mu m, respectively. The 3×3 array consisting of the asterisk-shaped radiating elements has implemented on the top silicon layer by applying the metasurface approach. Three slot lines in the ground-plane are modelled and located directly under the radiating elements. The radiating elements are excited through the slot-lines using an open-circuited microstrip-line constructed on the bottom silicon layer. The proposed method to excite the structure is based on the coupled feeding mechanism. In addition, by the proposed feeding method the on-chip antenna configuration supresses the substrate losses and surface-waves. The antenna exhibits a large impedance bandwidth of 60GHz from 0.5THz to 0.56THz with an average radiation gain and efficiency of 4.58dBi and 25.37%, respectively. The proposed structure has compact dimensions of 200×200×45μm3. The results shows that, the proposed technique is therefore suitable for on-chip antennas for applications in system-on-chip for terahertz (THz) integrated circuits.
AB - This paper proposes a new solution to improve the performance parameters of on-chip antenna designs on standard CMOS silicon (Si.) technology. The proposed method is based on applying the metasurface technique and exciting the radiating elements through coupled feed mechanism. The on-chip antenna is constructed from three layers comprising Si.-GND-Si. layers, so that the ground (GND) plane is sandwiched between two Si. layers. The silicon and ground-plane layers have thicknesses of 20mu m and 5mu m, respectively. The 3×3 array consisting of the asterisk-shaped radiating elements has implemented on the top silicon layer by applying the metasurface approach. Three slot lines in the ground-plane are modelled and located directly under the radiating elements. The radiating elements are excited through the slot-lines using an open-circuited microstrip-line constructed on the bottom silicon layer. The proposed method to excite the structure is based on the coupled feeding mechanism. In addition, by the proposed feeding method the on-chip antenna configuration supresses the substrate losses and surface-waves. The antenna exhibits a large impedance bandwidth of 60GHz from 0.5THz to 0.56THz with an average radiation gain and efficiency of 4.58dBi and 25.37%, respectively. The proposed structure has compact dimensions of 200×200×45μm3. The results shows that, the proposed technique is therefore suitable for on-chip antennas for applications in system-on-chip for terahertz (THz) integrated circuits.
KW - CMOS silicon (Si.) technology
KW - Coupled feeding mechanism
KW - Ground (GND)
KW - Metasurface
KW - On-chip antennas
KW - Terahertz (THz) systems-on-chip applications
KW - THz integrated circuits
UR - https://www.scopus.com/pages/publications/85082757097
U2 - 10.1109/APMC46564.2019.9038524
DO - 10.1109/APMC46564.2019.9038524
M3 - Conference Publication
AN - SCOPUS:85082757097
T3 - Asia-Pacific Microwave Conference Proceedings, APMC
SP - 246
EP - 248
BT - Proceedings of the 2019 IEEE Asia-Pacific Microwave Conference, APMC 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2019 IEEE Asia-Pacific Microwave Conference, APMC 2019
Y2 - 10 December 2019 through 13 December 2019
ER -