Multi-Phase Obfuscation of Fault Secured DSP Designs with Enhanced Security Feature

Digital signal processing (DSP) cores are an integral part of consumer electronics devices. This paper presents a novel methodology for obfuscation of transient fault secured circuits. The approach presented obfuscates fault secured DSP circuits such that the functions of the resulting hardware become non-obvious to an adversary (hindering reverse engineer process). The proposed methodology employs hybrid transformations in succession such as redundant operation removal, resource transformation, and connectivity change using tree height transformation, logic transformation, etc. These are achieved without affecting the functionality of the underlying DSP circuits or requiring significant increase in silicon footprint. The proposed methodology integrates an enhanced fault security feature using multi-cuts that ensures maximum detection capability against transient faults in the DSP circuit. Results of proposed approach indicate stronger obfuscation and enhanced fault security at lower design cost (avg. reduction 14%), compared to prior art.