Design & implementation of a novel low power hybrid full adder circuit

In this paper 1-bit hybrid full Adder is implemented using complementary metal-oxide-semiconductor (CMOS) logic and pass transistor logic. The circuit is implemented using Cadence Virtuoso tool in 180nm technology. Performance parameters like power and layout area were compared with existing designs such as complementary pass transistor logic, transmission gate adder, transmission function adder and so on. For 1.8 V supply static power consumption 477.3 pW and average power consumption is 3.617 uw which is comparatively lower than the existing designs. Even layout is implemented and its DRC, LVS and RC extraction is done. In comparison to the existing designs this design is better in terms of power and layout.