TY - GEN
T1 - An Optimised Constant-Time Implementation of KASUMI FI Function
AU - Urquhart, Emma
AU - Chambers, Desmond
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - Substitution boxes (S-boxes) are a key component of many modern ciphers and their optimization can contribute to significant overall performance improvements. Although often implemented as lookup tables, mathematically, many common S-boxes can be represented as non-linear, Boolean mappings. This property can be leveraged to efficiently compute S-box values in constant time, thereby securing implementations against timing attacks. We propose an acceleration method for one such S-box, that of the KASUMI cipher, and integrate it into the Intel(R) IPSec Multi-Buffer Library [9] implementation. The Kasumi algorithm is a block cipher, widely used in 3G mobile communication networks. It was specified for the 3rd Generation Partnership Project (3GPP) to ensure the confidentiality and integrity of wireless data communications, such as voice and data transmissions. Although the prevalence of 3G is declining, Kasumi remains in operation in legacy systems and is consequently still provided as part of the Intel(R) IPSec Multi-Buffer Library. The optimization techniques proposed demonstrate the acceleration capabilities of modern CPU architectures for parallel S-box computation (and the enclosing FI function in Kasumi) and may hold the potential for wider application to cryptographic algorithms which incorporate Boolean S-boxes. The proposed implementation is an optimised version of the existing constant-time implementation of KASUMI in the Intel(R) IPSec Multi-Buffer Library, improving performance by a factor of 9.47.
AB - Substitution boxes (S-boxes) are a key component of many modern ciphers and their optimization can contribute to significant overall performance improvements. Although often implemented as lookup tables, mathematically, many common S-boxes can be represented as non-linear, Boolean mappings. This property can be leveraged to efficiently compute S-box values in constant time, thereby securing implementations against timing attacks. We propose an acceleration method for one such S-box, that of the KASUMI cipher, and integrate it into the Intel(R) IPSec Multi-Buffer Library [9] implementation. The Kasumi algorithm is a block cipher, widely used in 3G mobile communication networks. It was specified for the 3rd Generation Partnership Project (3GPP) to ensure the confidentiality and integrity of wireless data communications, such as voice and data transmissions. Although the prevalence of 3G is declining, Kasumi remains in operation in legacy systems and is consequently still provided as part of the Intel(R) IPSec Multi-Buffer Library. The optimization techniques proposed demonstrate the acceleration capabilities of modern CPU architectures for parallel S-box computation (and the enclosing FI function in Kasumi) and may hold the potential for wider application to cryptographic algorithms which incorporate Boolean S-boxes. The proposed implementation is an optimised version of the existing constant-time implementation of KASUMI in the Intel(R) IPSec Multi-Buffer Library, improving performance by a factor of 9.47.
KW - information security
KW - Intel processors
KW - Kasumi
KW - S-boxes
KW - software optimization
UR - http://www.scopus.com/inward/record.url?scp=85201162813&partnerID=8YFLogxK
U2 - 10.1109/ISSC61953.2024.10603289
DO - 10.1109/ISSC61953.2024.10603289
M3 - Conference Publication
AN - SCOPUS:85201162813
T3 - Proceedings of the 35th Irish Systems and Signals Conference, ISSC 2024
BT - Proceedings of the 35th Irish Systems and Signals Conference, ISSC 2024
A2 - Zheng, Huiru
A2 - Cleland, Ian
A2 - Moore, Adrian
A2 - Wang, Haiying
A2 - Glass, David
A2 - Rafferty, Joe
A2 - Bond, Raymond
A2 - Wallace, Jonathan
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 35th Irish Systems and Signals Conference, ISSC 2024
Y2 - 13 June 2024 through 14 June 2024
ER -