Abstract
Electronic design tools and techniques for the implementation of a stereoscopic camera based on an FPGA (Field Programmable Gate Array) are presented. The stages of an IPP (Image Processing Pipeline) are presented together with the development tools and languages used to implement a stereoscopic camera in hardware. In a further development of the basic system, aspects of the implementation of a 3D camera are presented.
| Original language | English (Ireland) |
|---|---|
| Title of host publication | 9TH ROEDUNET IEEE INTERNATIONAL CONFERENCE |
| Publisher | LUCIAN BLAGA UNIV SIBIU, ROMANIA |
| Number of pages | 5 |
| Publication status | Published - 1 Jan 2010 |
Authors (Note for portal: view the doc link for the full list of authors)
- Authors
- Andorko, I;Corcoran, P;Bigioi, P