TY - GEN
T1 - Adaptive routing strategies for large scale spiking neural network hardware implementations
AU - Carrillo, Snaider
AU - Harkin, Jim
AU - McDaid, Liam
AU - Pande, Sandeep
AU - Cawley, Seamus
AU - Morgan, Fearghal
PY - 2011
Y1 - 2011
N2 - This paper presents an adaptive Network-on-Chip (NoC) router, which forms part of an embedded mixed signal Spiking Neural Network (SNN) architecture called EMBRACE (Emulating Biologically-inspiRed ArChitectures in hardware). The novel adaptive NoC router provides the inter-neuron connectivity for EMBRACE, maintaining router communication and avoiding dropped router packets by adapting to router traffic congestion. The router also adapts to NoC traffic congestion or broken NoC connections (faults) by reconfiguring the routing topology to select an alternative route. Performance, power and area analysis of the proposed adaptive router using Synopsys Design Compiler (for TSMC 90nm CMOS technology) indicates a router throughput of 3.2Gbps on each of 5 available router channels, low router power consumption (1.716mW) and small router area (0.056mm2). Router adaptive behaviour in the presence of applied real-time traffic congestion has been demonstrated on a Virtex II Pro Xilinx FPGA for a 4x2 router array. Results indicate the feasibility of using the proposed adaptive NoC router within a scalable EMBRACE hardware SNN architecture.
AB - This paper presents an adaptive Network-on-Chip (NoC) router, which forms part of an embedded mixed signal Spiking Neural Network (SNN) architecture called EMBRACE (Emulating Biologically-inspiRed ArChitectures in hardware). The novel adaptive NoC router provides the inter-neuron connectivity for EMBRACE, maintaining router communication and avoiding dropped router packets by adapting to router traffic congestion. The router also adapts to NoC traffic congestion or broken NoC connections (faults) by reconfiguring the routing topology to select an alternative route. Performance, power and area analysis of the proposed adaptive router using Synopsys Design Compiler (for TSMC 90nm CMOS technology) indicates a router throughput of 3.2Gbps on each of 5 available router channels, low router power consumption (1.716mW) and small router area (0.056mm2). Router adaptive behaviour in the presence of applied real-time traffic congestion has been demonstrated on a Virtex II Pro Xilinx FPGA for a 4x2 router array. Results indicate the feasibility of using the proposed adaptive NoC router within a scalable EMBRACE hardware SNN architecture.
KW - adaptive routing
KW - brain-inspired computing
KW - EMBRACE architecture
KW - fault-tolerant
KW - inter-neuron scalability
KW - network-on-chip
KW - Spiking neural networks
UR - https://www.scopus.com/pages/publications/79959340845
U2 - 10.1007/978-3-642-21735-7_10
DO - 10.1007/978-3-642-21735-7_10
M3 - Conference Publication
AN - SCOPUS:79959340845
SN - 9783642217340
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 77
EP - 84
BT - Artificial Neural Networks and Machine Learning, ICANN 2011 - 21st International Conference on Artificial Neural Networks, Proceedings
T2 - 21st International Conference on Artificial Neural Networks, ICANN 2011
Y2 - 14 June 2011 through 17 June 2011
ER -