TY - GEN
T1 - A dual image processing pipeline camera with CE applications
AU - Andorko, Istvan
AU - Corcoran, Peter
AU - Bigioi, Petronel
PY - 2011
Y1 - 2011
N2 - The implementation of a dual image processing pipeline camera on a state-of-art FPGA system is described. This camera can simultaneously acquire dual images of a scene and process, analyze and merge both images to enable a range of realtime image enhancement algorithms to be explored. Several examples of image enhancement algorithms implemented on the prototype camera are described.
AB - The implementation of a dual image processing pipeline camera on a state-of-art FPGA system is described. This camera can simultaneously acquire dual images of a scene and process, analyze and merge both images to enable a range of realtime image enhancement algorithms to be explored. Several examples of image enhancement algorithms implemented on the prototype camera are described.
UR - https://www.scopus.com/pages/publications/79952957399
U2 - 10.1109/ICCE.2011.5722837
DO - 10.1109/ICCE.2011.5722837
M3 - Conference Publication
AN - SCOPUS:79952957399
SN - 9781424487127
T3 - Digest of Technical Papers - IEEE International Conference on Consumer Electronics
SP - 737
EP - 738
BT - 2011 IEEE International Conference on Consumer Electronics, ICCE 2011
T2 - 2011 IEEE International Conference on Consumer Electronics, ICCE 2011
Y2 - 9 January 2011 through 12 January 2011
ER -