A dual image processing pipeline camera with CE applications

Istvan Andorko; Peter Corcoran; Petronel Bigioi

doi:10.13025/18757

A dual image processing pipeline camera with CE applications

Istvan Andorko
, Peter Corcoran
, Petronel Bigioi

Electrical & Electronic Engineering

Research output: Chapter in Book or Conference Publication/Proceeding › Conference Publication › peer-review

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Abstract

The implementation of a dual image processing pipeline camera on a state-of-art FPGA system is described. This camera can simultaneously acquire dual images of a scene and process, analyze and merge both images to enable a range of real-time image enhancement algorithms to be explored. Several examples of image enhancement algorithms implemented on the prototype camera are described.

Original language	English (Ireland)
Title of host publication	Consumer Electronics (ICCE), 2011 IEEE International Conference on
Number of pages	1
DOIs	https://doi.org/10.13025/18757
Publication status	Published - 1 Jan 2011

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10.13025/18757Licence: CC BY-NC-ND

Dual pipeline camera PC V02Accepted author manuscript, 4.88 MBLicence: CC BY-NC-ND

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@inproceedings{15daa63a02604f098c6bab86303e9bdb,

title = "A dual image processing pipeline camera with CE applications",

abstract = "The implementation of a dual image processing pipeline camera on a state-of-art FPGA system is described. This camera can simultaneously acquire dual images of a scene and process, analyze and merge both images to enable a range of real-time image enhancement algorithms to be explored. Several examples of image enhancement algorithms implemented on the prototype camera are described.",

author = "Istvan Andorko and Peter Corcoran and Petronel Bigioi",

year = "2011",

month = jan,

day = "1",

doi = "10.13025/18757",

language = "English (Ireland)",

booktitle = "Consumer Electronics (ICCE), 2011 IEEE International Conference on",

}

TY - GEN

T1 - A dual image processing pipeline camera with CE applications

AU - Andorko, Istvan

AU - Corcoran, Peter

AU - Bigioi, Petronel

PY - 2011/1/1

Y1 - 2011/1/1

N2 - The implementation of a dual image processing pipeline camera on a state-of-art FPGA system is described. This camera can simultaneously acquire dual images of a scene and process, analyze and merge both images to enable a range of real-time image enhancement algorithms to be explored. Several examples of image enhancement algorithms implemented on the prototype camera are described.

AB - The implementation of a dual image processing pipeline camera on a state-of-art FPGA system is described. This camera can simultaneously acquire dual images of a scene and process, analyze and merge both images to enable a range of real-time image enhancement algorithms to be explored. Several examples of image enhancement algorithms implemented on the prototype camera are described.

UR - http://hdl.handle.net/10379/3665

U2 - 10.13025/18757

DO - 10.13025/18757

M3 - Conference Publication

BT - Consumer Electronics (ICCE), 2011 IEEE International Conference on

ER -

A dual image processing pipeline camera with CE applications

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